[ao16aprs] RE: Cheap Modem

["Schayk A.H. van" <A.H.Schayk@arcadis.nl>]

>From the jas-1 modem discription:

The carrier recovery circuit used here is a digital "squaring loop"

U4 (TL084 opamp) pins 2,3,1 is a limiter, which simply makes all subsequent
signal processing digital.
The limited signal is multiplied by itself delayed by 1/4 cycle. The dely is
provided by 4 bit shift register U8 which samples the signal at its pin 7,
and is clocked at 16x carrier frequency. The multiplication happens in EXOR
gate U7 pins 5,6. This creates (at U7 pin 4) one cycle of twice the carrier
frequency for every zero crossing of the signal. Mathematically we can say
the signal is Cos(wt+-pi/2), the + or - corresponding to date 0 or 1. So the
effect of this multiplication is (ignoring amplitude):
	Cos(wt+-pi/2) x Sin(wt+-pi/2)  => Sin(2wt+-pi) => Sin(2wt)
	   Signal         x   Delayed      =>    constant phase at 2w

The phase locked loop U11 (4046) runs 16x carrier frequency; with associated
divide-by-16 U9 (40161) they lock onto U7 pin 4's double frequency signal,
providing a smooth recoveryd carrier at U9 pin 11.

end quote

it looks to me that the pll is pulled to the audio and not the audio to the
pll but i may be mistaking

73 de Andre PE1RDW

> -----Oorspronkelijk bericht-----
> Van:	Darryl Smith [SMTP:vk2tds@ozemail.com.au]
> Verzonden:	vrijdag 10 september 1999 7:05
> Aan:	TAPR AO-16 APRS Special Interest Group
> Onderwerp:	[ao16aprs] RE: Cheap Modem
> 
> Hi there...
> 
> If it is the design I am thinking of, STAY AWAY... The unit uses a digital
> PLL, and rectifies the incoming audio to put into the PLL... From memory
> it
> is about 3dB worse than any other design
> 
> Darryl
> 
> ---------
> Darryl Smith, VK2TDS   POBox 169 Ingleburn NSW 2565 Australia
> Mobile Number 0412 929 634 [+61 4 12 929 634 International]
> 
> 
> 
> 
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